The related art discloses non-volatile magnetic random access memory (MRAM) cells that are positioned in an array 10, as illustrated in FIG. 1. The array 10 includes a plurality of word lines 20 that extend along rows of the array 10 and a plurality of bit lines 30 that extend along columns of the array 10. The word lines 20 and bit lines 30 criss-cross each other and intersect. Between the word lines 20 and bit lines 30, at locations where they intersect, are included MRAM memory cells 40 that each include a magnetic tunnel junction (MTJ) 50 and a silicon junction diode 60 (illustrated in FIG. 2).
FIG. 2 illustrates a side perspective view of an MRAM memory cell 40 as disclosed in the related art. FIG. 2 shows an n-type silicon layer 70 in contact with a word line 20 (not shown). On top of the n-type silicon layer 70 is a p-type silicon layer 80 that, together with the n-type silicon layer 70, make up the silicon junction diode 60. Adjacent to this silicon junction diode 60 is formed a tungsten stud layer 90 and a template layer 100. Above the template layer 100 are a ferromagnetic layer 110, an anti-ferromagnetic layer 120, a fixed ferromagnetic layer 130, a tunneling barrier layer 140, a soft ferromagnetic layer 150, and a contact layer 160 that provides an electrical contact to a bit line 30 (shown in FIG. 1).
In operation, the MRAM memory cell 40 has data bits written to it and read from it. Initially, the MRAM memory cell 40 may be in a first resistance state, also known as a parallel state, where the soft ferromagnetic layer 150 is in a first direction of magnetization that is the same direction of magnetization as that of the fixed ferromagnetic layer 130. Alternately, the MRAM memory cell 40 may be in a second resistance state, also known as an anti-parallel state, where the soft ferromagnetic layer 150 is in a second direction of magnetization that is different from the direction of magnetization of the fixed ferromagnetic layer 130.
When writing to an MRAM memory cell 40 in the array 10, potentials are applied to both the word line 20 and bit line 30 that are adjacent to the MRAM memory cell 40. These potentials generate currents that travel through the word line 20 and the bit line 30 to which they are applied. These currents, in turn, generate magnetic fields that are coupled to the selected MRAM memory cell 40 and that are of a sufficient combined magnitude to alter the direction of magnetization of the soft ferromagnetic layer 150. Hence, when being written to, the MRAM memory cell 40 may experience a measurable increase in resistance if the coupled magnetic fields change the cell 40 from the first resistance state to the second resistance state. On the other hand, if the MRAM memory cell 40 is changed, by the coupled magnetic fields, from the second resistance state to the first resistance state, the cell 40 will experience a measurable decrease in resistance.
In other words, the resistance of an MRAM memory cell 40 is a function of the relative directions of magnetization of the fixed ferromagnetic layer 130 and of the soft ferromagnetic layer 150. When the directions of magnetization are parallel, the resistance is measurably lower than the when the directions of magnetization are anti-parallel.
During a reading step, the resistance of the MRAM memory cell 40 is detected by passing an amount of current through the MRAM memory cell 40. Then, the resistance of the cell 40 is monitored and, by sensing whether the MRAM memory cell 40 is in a high resistance state or a low resistance state, it is possible to determine whether the MRAM memory cell 40 is in the parallel or anti-parallel state. In other words, it is possible to determine whether the MRAM memory cell 40 contains a “0” data bit or a “1” data bit.
Among the disadvantages of the devices illustrated in FIGS. 1 and 2 is the fact that many diodes 60 and MRAM memory cells 40 are typically included in an array 10 and that the diodes 60 and MRAM memory cells 40 may not have a tight distributions of resistances values. Hence, what may be a resistance value for the high resistance state in one MRAM memory cell 40 may be the resistance value for the low resistance state in another MRAM memory cell 40. In the absence of a tight distribution of resistances values, the data bits in the MRAM memory cells 40 may be read erroneously.